1. Field of the Invention
The present invention generally relates to semiconductor memory devices and memory systems, and particularly relates to a semiconductor memory device and memory system in which refresh can be performed with respect to part of the memory area.
2. Description of the Related Art
In portable terminals such as portable phones, SRAM (Static Random Access Memory) has conventionally been used. In recent years, there has been a trend to use DRAM (Dynamic Random Access Memory) for the purpose of providing a large memory capacity. With such configuration, the operating time of the battery becomes a problem.
SRAM consumes almost no electric power for the purpose of data retention. DRAM, on the other hand, stores data in memory capacitors, and requires that a refresh be periodically performed in order to retain the data. In DRAM used in potable equipment, generally, automatic refresh is internally performed based on a self-refresh function. The DRAM refresh operation includes reading cell data by successively activating word selecting lines, amplifying the data voltage by use of sense amplifiers, and restoring the amplified data to the cells. As a result, each refresh operation ends up consuming electric currents. DRAM thus consumes some electric power even in the standby mode. Namely, the retention of data in memory consumes electric power even when the portable equipment is not being used, thereby shortening the usable time of the battery.
In consideration of this, the self-refresh function of DRAM embedded in portable equipment is provided with a partial refresh function. The partial refresh function serves to perform a refresh operation only with respect to a portion of the DRAM memory area that requires refresh for the retention of data. When portable equipment shifts from the active mode to the standby mode, for example, the memory area used as a work area during the active mode does not need to retain data in the standby mode. It is thus possible to eliminate the refresh operation for such memory area.
FIG. 1 is a drawing illustrating a DRAM memory area. In FIG. 1, a DRAM memory area 10 includes 8 blocks 11-1 through 11-8, for example. For the sake of simplicity of explanation, it is assumed that the memory array of each block includes 8 word lines. Depending on the circumstances, the partial refresh function may perform the refresh operation only with respect to only one block 11-1, for example, or may perform the refresh operation only with respect to two blocks 11-1 and 11-2.
FIG. 2 is a drawing for explaining the partial refresh operation. FIG. 2-(a) shows word lines subjected to successive refreshes when the entirety of the DRAM memory area 10 is refreshed. Word lines WL0 through WL7 are the eight word lines of the block 11-1, for example, and word lines WL8 through WL15 (illustrated up to WL11) are the eight word lines of the block 11-2. In the same manner, each one of the blocks 11-3 through 11-8 is provided with eight word lines.
When the entirety of the DRAM memory area 10 is refreshed as shown in FIG. 2-(a), the eight word lines WL0 through WL7 of the block 11-1 are successively activated and subjected to refresh operation, followed by the word lines WL8 through WL15 of the block 11-2 being successively activated and subjected to refresh operation. Thereafter, the blocks 11-3 through 11-8 are successively subjected to refresh operation, followed by the block 11-1 being refreshed again for the next round of refresh operation.
FIG. 2-(b) shows the word lines subjected to successive refreshes when only the block 11-1 of the DRAM memory area 10 is refreshed. The word line WL0 of the block 11-1 is refreshed first, and, then, the next word line. WL1 of the same block 11-1 is refreshed after an interval that is longer than in the case of (a). Thereafter, the word lines WL2 through WL7 of the block 11-1 are refreshed in the same manner, followed by the word line WL0 being refreshed again for the next round of refresh operation. In the case of (b), the number of word lines subjected to refresh is ⅛ of the total number of word lines of the DRAM memory area 10, so that the refresh interval can be set ⅛ as frequent as the interval used in the case of (a). With such setting, the time length from the refreshing of the word line WL0 to the next refreshing of the same word line WL0 is the same between the case (a) and the case (b).
FIG. 2-(c) shows the word lines subjected to successive refreshes when only the blocks 11-1 and 11-2 of the DRAM memory area 10 are refreshed. The word line WL0 of the block 11-1 is refreshed first, and, then, the next word line WL1 of the same block 11-1 is refreshed after an interval that is longer than in the case of (a) but shorter than in the case of (b). Thereafter, the word lines WL2 through WL7 of the block 11-1 are refreshed in the same manner, and, then, the word lines WL8 through WL15 of the block 11-2 are refreshed. After this, the word line WL0 of the block 11-1 is refreshed again for the next round of refresh operation. In the case of (c), the number of word lines subjected to refresh is ¼ of the total number of word lines of the DRAM memory area 10, so that the refresh interval can be set ¼ as frequent as the interval used in the case of (a). With such setting, the time length from the refreshing of the word line WL0 to the next refreshing of the same word line WL0 is the same between the case (a) and the case (c).
With the arrangement as shown in FIG. 2, it is possible to achieve the partial refresh function. This arrangement, however, gives rise to a problem as follows when a transition occurs from the ⅛ partial refresh operation (FIG. 2-(b)) to the ¼ partial refresh operation (FIG. 2-(c)).
In the ⅛ partial refresh operation, adjacent word lines are refreshed at time interval T, for example, and the same word line is refreshed at time interval 8T. There may be a case in which a transition occurs from the ⅛ partial refresh operation (FIG. 2-(b)) to the ¼ partial refresh operation (FIG. 2-(c)) upon refreshing the word lines WL0 through WL6, for example. The next word line to be refreshed is WL7, so that the word line WL7 is refreshed, followed by refreshing the word lines WL8 through WL15 in the order of address. In this case, more than 8T ends up passing before the word line WL0 is refreshed again. Namely, the data of the memory cells corresponding to the word line WL0 are not refreshed within the time period necessary to retain data, so that the data may end up being lost.
In order to avoid this problem, there is a need to perform a refresh operation at an interval shorter than normal refresh interval T/2 corresponding to the ¼ partial refresh operation after the transition to the ¼ partial refresh operation (FIG. 2-(c)). With such behavior, high-speed refresh operation (i.e., refreshes at short intervals) is necessary each time the refresh area is changed. This causes an increase in electric current consumption.
[Patent Document 1] International Publication No. WO04/070729
Accordingly, there is a need for a semiconductor memory device provided with a partial refresh function that can reliably retain data through refresh operation without causing an increase in electric current consumption.